This invention relates generally to switched capacitor circuits and more particularly to circuits adapted to store charge on a sampling capacitor related to a sample of an analog signal voltage during a charging, or sampling phase and to transfer the stored charge to an output during a charge transfer phase.
As is known in the art, switched capacitor circuits have a variety of applications. For example, in analog to digital converters (ADCs) which are based on either capacitor digital to analog converters (DACs) or oversampling schemes, such as sigma-delta converters, an interface is typically required between the analog input signal voltage being converted into corresponding digital samples and the conversion architecture. The interface typically samples the analog signal voltage and stores such sampled voltage as a corresponding, proportional charge on a sampling capacitor. More particularly, the interface is provided between the analog voltage signal and the sampling capacitor. After storage, the stored charge is converted into a corresponding digital signal representative of the sampled analog input signal voltage by the conversion architecture. In a sigma-delta ADC architecture, the charge is stored on the sampling capacitor during a charging phase and is transferred to an output during a charge transfer phase for conversion. This charging/charge transfer phasing is provided by a switched capacitor circuit.
More particularly, as shown in FIG. 1 and as described in U.S. Pat. No. 5,134,401 issued Jul. 28, 1992 entitled "Delta Sigma Modulator Having Programmable Gain/Attenuation", inventors McCartney et al., assigned to the same assignee as the present invention, the subject matter thereof being incorporated by reference, the switched capacitor circuit 10 includes a sampling capacitor Cs and four transistors m1, m2, m3 and m4. The output of the switched capacitor circuit 10 is coupled to a summing node n3. During the charging phase, control signal Ph2 (FIG. 2B) at the gate electrodes of transistors m1, m2 places transistors m1and m3 in a conducting condition and control signal Ph1 (FIG. 2A) at the gate electrodes of transistors m2, m3 places transistors m2 and m3 in a non-conducting condition. Thus, a charge packet, Cs*Vin is stored on sampling capacitor Cs at the end of the charging phase, where Vin is the analog input signal voltage. During the charge transfer phase, control signal Ph1 switches transistors m1 and m3 to the non-conducting condition and control signal Ph1 places transistors m2 and m3 in the conducting condition thereby transferring the charge packet stored on the sampling capacitor Cs to the summing node n3.
It should be noted that while the circuit in FIG. 1 is for a single ended analog input signal voltage for simplification, the actual implementation may be a fully differential analog input signal voltage. Thus, with this understanding, transistors m2 and m3 are connected to a reference voltage, VREF. The summing node n3 is at one input of an operational amplifier A1, say the non-inverting input, and the reference voltage VREF is at the other input, say the inverting input, of the operational amplifier A1. The reference voltage VREF is typically the common mode, or mid-range voltage of the analog input signal voltage. Thus, when the analog input signal voltage is a unipolar voltage (i.e., a voltage which varies with one polarity relative to ground potential, either a positive (+) voltage or a negative (-) voltage), VREF would be +2.5 volts.
In operation, when the analog input signal voltage is at the +2.5 volt, mid-range voltage, it is noted that node n1 is at this mid-range +2.5 volt level during both the charging phase and the charge transfer phase. Thus, there will be no net charge to the integrating capacitor when the analog input signal voltage is at the mid-range voltage. It should also be noted that when transistor m3 is in conduction during the charging phase, the voltage at the summing node n3 is equal to the reference voltage VREF at the other input to the operational amplifier A1.
It should be noted that, in some applications the analog input signal voltage to be converted into digital samples is produced as a bipolar voltage signal (i.e., a voltage which varies with both polarities relative to ground, both positive (+) and negative (-) voltages). In other applications, the analog signal is produced as a unipolar signal and is then fed to a signal conditioning circuit. The signal conditioning circuit may provide amplification and filtering to the analog input signal voltage. These signal conditioning circuits are usually easier, and less expensive to design when a bipolar voltage supply is used. A bipolar supply is a zero, or ground based voltage supply which provides a positive voltage (i.e., a voltage above ground) and a negative voltage (i.e., a voltage below ground). The conditioned signal, which has voltages above and below ground is then passed to the analog to digital converter (ADC). While the signal conditioning circuits are usually less expensive when a bipolar voltage supply is used, the ADC is typically less expensive when a unipolar, (i.e., 0 to 5 volt supply) is used. More particularly, it may be advantageous to use complementary metal oxide silicon (CMOS) transistor technology in fabricating the ADC and supplying the CMOS ADC with the unipolar voltage supply. Thus, if a bipolar voltage supply is used for the signal conditioning circuitry, the ADC, unipolar powered CMOS circuitry is now fed with a bipolar analog input signal voltage, i.e., the range of analog input signal voltages fed to the ADC will be both above and below ground.
It should be noted that if transistor m1 included a nMOS transistor within an n-type conductivity well of the semiconductor substrate, when the analog input signal voltage is negative, the analog input signal voltage would be clamped to the grounded substrate (i.e., the analog input signal voltage would be diode clamped to the grounded substrate). If a pMOS transistor were used for m1, while a negative analog input signal voltage would not produce diode clamping as with the NMOS transistor, a voltage several volts (i.e., about 2 volt) below the analog input signal voltage would be required at the gate electrode of transistor m1 to turn such transistor m1 to the conduction condition. Thus, when the analog input signal voltage is below ground, i.e., negative, a negative voltage is required at the gate electrode of transistor m1 to place such transistor m1 in the conducting condition. One technique used to provide such negative voltage is to use a bipolar voltage supply. Another technique is to shifted the voltage of the analog input signal voltage so that the voltage range fed to transistor m1 will only vary above ground; i.e., so that the voltage fed to transistor m1 will vary from +1.0 volts to +4.0 volts with VREF being +2.5 volts. One technique used to provide such voltage level shift to the analog input signal voltage is to provide a level shifting voltage. However, such level shifting voltage may tend to change with temperature and noise; unlike a more stable ground.